Cite
HARVARD Citation
Corsonello, P. et al. (n.d.). Gate‐level body biasing technique for high‐speed sub‐threshold CMOS logic gates. International journal of circuit theory and applications. pp. 65-70. [Online].
This is an interim version of our Electronic Legal Deposit Catalogue-eJournals and eBooks while we continue to recover from a cyber-attack.
Corsonello, P. et al. (n.d.). Gate‐level body biasing technique for high‐speed sub‐threshold CMOS logic gates. International journal of circuit theory and applications. pp. 65-70. [Online].