Gate‐level body biasing technique for high‐speed sub‐threshold CMOS logic gates. (1st August 2012)

• Record Type: Journal Article
• Authors: Corsonello, P.; Lanuzza, M.; Perri, S.
• Is Part Of: International journal of circuit theory and applications. Volume 42:Number 1(2014:Jan.)
• Page Start: 65
• Page End: 70
• Publication Date: 2012-08-01
• Subjects: Electric circuit analysis -- Periodicals; 621.319205
• DOI: 10.1002/cta.1838
• Languages: English
• ISSNs: 0098-9886

Abstract

<abstract abstract-type="main"> <title> <x xml:space="preserve">Abstract</x> </title> <p>An efficient technique for designing high‐performance logic circuits operating in sub‐threshold region is proposed. A simple gate‐level body biasing circuit is exploited to change dynamically the threshold voltage of transistors on the basis of the gate status. Such an auxiliary circuit prepares the logic gate for fast switching while maintaining energy efficiency.</p> <p>If 200 aJ is the target total energy per operation consumption, a two input NAND (NOR) gate designed as described here shows a delay reduction between 20% (16%) and 40% (48%), with respect to previously proposed sub‐threshold approaches. Copyright 2012 John Wiley &amp; Sons, Ltd.</p> </abstract>