Design for embedded image processing on FPGAs. (2023)

• Record Type: Book
• Further Information: Note: By Donald G. Bailey.
• Authors: Bailey, Donald G (Donald Graeme), 1962-
• Contents: Preface xiii Acknowledgments xix About the Companion Website xxi 1 Image Processing 1 1.1 Basic Definitions 1 1.2 Image Formation 3 1.2.1 Optics 3 1.2.2 Colour 5 1.3 Image Processing Operations 6 1.4 Real-time Image Processing 8 1.5 Embedded Image Processing 9 1.6 Computer Architecture 10 1.7 Parallelism 11 1.7.1 Temporal or Task Parallelism 12 1.7.2 Spatial or Data Parallelism 13 1.7.3 Logical Parallelism 14 1.7.4 Stream Processing 14 1.8 Summary 15 References 16 2 Field-programmable Gate Arrays 19 2.1 Hardware Architecture of FPGAs 19 2.1.1 Logic 21 2.1.2 DSP Blocks 22 2.1.3 Memory 23 2.1.4 Embedded CPU 23 2.1.5 Interconnect 24 2.1.6 Input and Output 24 2.1.7 Clocking 26 2.1.8 Configuration 26 2.1.9 FPGAs vs. ASICs 27 2.2 Programming FPGAs 28 2.2.1 Register Transfer Level 30 2.2.2 Hardware Description Languages 32 2.2.3 High-level Synthesis 33 2.3 FPGAs and Image Processing 38 2.3.1 Choosing an FPGA or Development Board 39 2.4 Summary 40 References 41 3 Design Process 45 3.1 Problem Specification 45 3.2 Algorithm Development 47 3.2.1 Algorithm Development Process 47 3.2.2 Algorithm Structure 48 3.2.3 FPGA Development Issues 51 3.3 Architecture Selection 51 3.3.1 System Architecture 52 3.3.2 Partitioning Between Hardware and Software 53 3.3.3 Computational Architecture 55 3.4 System Implementation 60 3.4.1 Mapping to FPGA Resources 60 3.4.2 Algorithm Mapping Issues 62 3.5 Testing and Debugging 63 3.5.1 Design 63 3.5.2 Implementation 64 3.5.3 Common Implementation Bugs 64 3.5.4 Timing 66 3.5.5 System Debugging 68 3.5.6 Algorithm Tuning 70 3.5.7 In-field Diagnosis 71 3.6 Summary 72 References 73 4 Design Constraints 77 4.1 Timing Constraints 77 4.1.1 Low-level Pipelining 78 4.1.2 Process Synchronisation 80 4.1.3 Synchronising Between Clock Domains 82 4.1.4 I/O Constraints 83 4.2 Memory Bandwidth Constraints 84 4.2.1 Memory Architectures 84 4.2.2 Caching 86 4.2.3 Row Buffering 87 4.3 Resource Constraints 88 4.3.1 Bit-serial Computation 89 4.3.2 Resource Multiplexing 89 4.3.3 Arbitration 92 4.3.4 Resource Controllers 94 4.3.5 Reconfigurability 95 4.4 Power Constraints 97 4.5 Performance Metrics 98 4.5.1 Speed 99 4.5.2 Resources 99 4.5.3 Power 99 4.5.4 Cost 100 4.5.5 Application Metrics 100 4.6 Summary 101 References 102 5 Computational Techniques 105 5.1 Number Systems 105 5.1.1 Binary Integers 105 5.1.2 Residue Systems 106 5.1.3 Redundant Representations 107 5.1.4 Fixed-point Numbers 107 5.1.5 Floating-point Numbers 108 5.1.6 Logarithmic Number System 110 5.1.7 Posit Numbers 110 5.2 Elementary Functions 111 5.2.1 Square Root 111 5.2.2 Trigonometric Functions 112 5.2.3 Linear CORDIC 116 5.2.4 Hyperbolic Functions 117 5.2.5 Logarithms and Exponentials 118 5.2.6 Lookup Tables 118 5.2.7 Polynomial Approximations 122 5.2.8 Iterative Techniques 123 5.3 Other Computation Techniques 124 5.3.1 Incremental Update 124 5.3.2 Separability 124 5.4 Memory Structures 124 5.4.1 FIFO Buffer 124 5.4.2 Zigzag Buffers 126 5.4.3 Stacks 126 5.4.4 Linked Lists 127 5.4.5 Trees 128 5.4.6 Graphs 129 5.4.7 Hash Tables 129 5.5 Summary 130 References 131 6 Interfacing 135 6.1 Camera Input 135 6.1.1 Analogue Video 136 6.1.2 Direct Digital Interface 137 6.1.3 MIPI Camera Serial Interface 138 6.1.4 Camera Link 139 6.1.5 USB Cameras 139 6.1.6 GigE Vision 139 6.1.7 Camera Processing Pipeline 140 6.2 Display Output 143 6.2.1 Display Driver 143 6.2.2 Display Content 146 6.3 Serial Communication 147 6.3.1 Rs- 232 147 6.3.2 I 2 c 148 6.3.3 Serial Peripheral Interface (SPI) 149 6.3.4 Universal Serial Bus (USB) 150 6.3.5 Ethernet 150 6.3.6 PCI Express 151 6.4 Off-chip Memory 151 6.4.1 Static RAM 152 6.4.2 Dynamic RAM 152 6.4.3 Flash Memory 155 6.5 Processors 155 6.5.1 AXI Interface 155 6.5.2 Avalon Bus 156 6.5.3 Operating Systems 157 6.5.4 Implications for System Design 157 6.6 Summary 157 References 158 7 Point Operations 161 7.1 Point Operations on a Single Image 161 7.1.1 Contrast and Brightness Adjustment 161 7.1.2 Global Thresholding and Contouring 164 7.1.3 Lookup Table Implementation 166 7.2 Point Operations on Multiple Images 167 7.2.1 Image Averaging 168 7.2.2 Image Subtraction 170 7.2.3 Background Modelling 172 7.2.4 Intensity Scaling 175 7.2.5 Masking 175 7.2.6 High Dynamic Range (HDR) Imaging 177 7.3 Colour 179 7.3.1 False Colour 179 7.3.2 Colour Space Conversion 180 7.3.3 Colour Thresholding 192 7.3.4 Colour Enhancement 193 7.3.5 White Balance 194 7.4 Multi-spectral and Hyperspectral Imaging 197 7.4.1 Hyperspectral Image Acquisition 197 7.4.2 Processing Steps 198 7.5 Summary 199 References 199 8 Histogram Operations 203 8.1 Greyscale Histogram 203 8.1.1 Building the Histogram 203 8.1.2 Data Gathering 205 8.1.3 Histogram Equalisation 209 8.1.4 Automatic Exposure 214 8.1.5 Threshold Selection 215 8.1.6 Histogram Similarity 220 8.2 Multidimensional Histograms 220 8.2.1 Triangular Arrays 221 8.2.2 Multidimensional Statistics 222 8.2.3 Colour Segmentation 225 8.2.4 Colour Indexing 228 8.2.5 Texture Analysis 229 8.3 Summary 231 References 231 9 Local Filters 235 9.1 Window Caching 235 9.1.1 Border Handling 237 9.1.2 Filter Latency 239 9.2 Linear Filters 239 9.2.1 Filter Techniques 240 9.2.2 Noise Smoothing 243 9.2.3 Edge Detection 246 9.2.4 Edge Enhancement 248 9.3 Nonlinear Filters 249 9.3.1 Gradient Magnitude 249 9.3.2 Edge Orientation 250 9.3.3 Peak Detection and Non-maximal Suppression 251 9.3.4 Zero-crossing Detection 252 9.3.5 Bilateral Filter 252 9.3.6 Adaptive Thresholding 253 9.3.7 High Dynamic Range Tone Mapping 255 9.4 Rank Filters 256 9.4.1 Sorting Networks 258 9.5 Adaptive Histogram Equalisation 262 9.6 Morphological Filters 262 9.6.1 Binary Morphology 262 9.6.2 Greyscale Morphology 266 9.7 Colour Filtering 268 9.7.1 Colour Morphology and Vector Median 269 9.7.2 Edge Enhancement 269 9.7.3 Bayer Pattern De
• Edition: Second edition
• Publisher Details: Hoboken : John Wiley & Sons, Inc
• Publication Date: 2023
• Extent: 1 online resource (496 pages)
• Subjects: 621.3815; Field programmable gate arrays -- Design and construction; Image processing
• Languages: English
• ISBNs: 9781119819813
• Notes: Note: Description based on CIP data; resource not viewed.
• Access Rights: Legal Deposit; Only available on premises controlled by the deposit library and to one user at any one time; The Legal Deposit Libraries (Non-Print Works) Regulations (UK).
• Access Usage: Restricted: Printing from this resource is governed by The Legal Deposit Libraries (Non-Print Works) Regulations (UK) and UK copyright law currently in force.