Logic synthesis and SOC prototyping : RTL design using VHDL /: RTL design using VHDL. ([2020])
- Record Type:
- Book
- Title:
- Logic synthesis and SOC prototyping : RTL design using VHDL /: RTL design using VHDL. ([2020])
- Main Title:
- Logic synthesis and SOC prototyping : RTL design using VHDL
- Further Information:
- Note: Vaibbhav Taraate.
- Authors:
- Taraate, Vaibbhav
- Contents:
- Introduction -- ASIC Design and SOC prototype -- Design using VHDL & Guidelines -- Design using VHDL & Guidelines -- Design and Verification Strategies -- VHDL Design and RTL Tweaks -- ASIC Synthesis and Design Constraints -- Design optimization -- Design optimization -- FPGA for SOC Prototype -- Prototype using Single and Multiple FPGA.
- Publisher Details:
- Gateway East, Singapore : Springer
- Publication Date:
- 2020
- Copyright Date:
- 2020
- Extent:
- 1 online resource (XIX, 251 pages)
- Subjects:
- 621.3815
Systems on a chip
VHDL (Computer hardware description language)
Systems on a chip
VHDL (Computer hardware description language)
Electronic books - Languages:
- English
- ISBNs:
- 9811513147
9789811513145 - Notes:
- Note: Print version record.
- Access Rights:
- Legal Deposit; Only available on premises controlled by the deposit library and to one user at any one time; The Legal Deposit Libraries (Non-Print Works) Regulations (UK).
- Access Usage:
- Restricted: Printing from this resource is governed by The Legal Deposit Libraries (Non-Print Works) Regulations (UK) and UK copyright law currently in force.
- View Content:
- Available online (eLD content is only available in our Reading Rooms) ↗
- Physical Locations:
- British Library HMNTS - ELD.DS.481565
- Ingest File:
- 03_033.xml