Cite
HARVARD Citation
Taraate, V. (2019) Advanced HDL synthesis and SOC prototyping : RTL design using Verilog. [Online]. Singapore : Springer. Available from: http://access.bl.uk/ark:/81055/vdc_100078643000.0x000001
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Taraate, V. (2019) Advanced HDL synthesis and SOC prototyping : RTL design using Verilog. [Online]. Singapore : Springer. Available from: http://access.bl.uk/ark:/81055/vdc_100078643000.0x000001