Advances in embedded and fan-out wafer level packaging technologies. (2019)

• Record Type: Book
• Further Information: Note: Edited by Beth Keser, Steffen Kroehnert.
• Editors: Keser, Beth, 1971-; Kroehnert, Steffen, 1970-
• Contents: Preface xvii List of Contributors xxiii Acknowledgments xxvii 1 History of Embedded and Fan‐Out Packaging Technology 1; Michael Topper, Andreas Ostmann, Tanja Braun, and Klaus‐Dieter Lang 2 FO‐WLP Market and Technology Trends 39; E. Jan Vardaman 3 Embedded Wafer‐Level Ball Grid Array (eWLB) Packaging Technology Platform 55; Thorsten Meyer and Steffen Krohnert 4 Ultrathin 3D FO‐WLP eWLB‐PoP (Embedded Wafer‐Level Ball Grid Array‐Package‐on‐Package) Technology 77; S.W. Yoon 5 NEPES’ Fan‐Out Packaging Technology from Single die, SiP to Panel‐Level Packaging 97; Jong Heon (Jay) Kim 6 M‐Series™ Fan‐Out with Adaptive Patterning™ 117; Tim Olson and Chris Scanlan 7 SWIFTR Semiconductor Packaging Technology 141; Ron Huemoeller and Curtis Zwenger 8 Embedded Silicon Fan‐Out (eSiFOR) Technology for Wafer‐Level System Integration 169; Daquan Yu 9 Embedding of Active and Passive Devices by Using an Embedded Interposer: The i2 Board Technology 185; Thomas Gottwald, Christian Roessle, and Alexander Neumann 10 Embedding of Power Electronic Components: The Smart p2 Pack Technology 201; Thomas Gottwald and Christian Roessle 11 Embedded Die in Substrate (Panel‐Level) Packaging Technology 217; Tomoko Takahashi and Akio Katsumata 12 Blade: A Chip‐First Embedded Technology for Power Packaging 241; Boris Plikat and Thorsten Scharf 13 The Role of Liquid Molding Compounds in the Success of Fan‐Out Wafer‐Level Packaging Technology 261; Katsushi Kan, Michiyasu Sugahara, and Markus Cichon 14 Advanced Dielectric Materials (Polyimides and Polybenzoxazoles) for Fan‐Out Wafer‐Level Packaging (FO‐WLP) 271; T. Enomoto, J.I. Matthews, and T. Motobe 15 Enabling Low Temperature Cure Dielectrics for Advanced Wafer‐Level Packaging 317; Stefan Vanclooster and Dimitri Janssen 16 The Role of Pick and Place in Fan‐Out Wafer‐Level Packaging 347; Hugo Pristauz, Alastair Attard, and Harald Meixner 17 Process and Equipment for eWLB: Chip Embedding by Molding 371; Edward Furgut, Hirohito Oshimori, and Hiroaki Yamagishi 18 Tools for Fan‐Out Wafer‐Level Package Processing 403; Nelson Fan, Eric Kuah, Eric Ng, and Otto Cheung 19 Equipment and Process for eWLB: Required PVD/Sputter Solutions 419; Chris Jones, Ricardo Gaio, and Jose Castro 20 Excimer Laser Ablation for the Patterning of Ultra‐fine Routings 441; Habib Hichri, Markus Arendt, and Seongkuk Lee 21 Temporary Carrier Technologies for eWLB and RDL‐First Fan‐Out Wafer‐Level Packages 457; Thomas Uhrmann and Boris Pova?ay 22 Encapsulated Wafer‐Level Package Technology (eWLCSP): Robust WLCSP Reliability with Sidewall Protection 471; S.W. Yoon 23 Embedded Multi‐die Interconnect Bridge (EMIB): A Localized, High Density, High Bandwidth Packaging Interconnect 487; Ravi Mahajan, Robert Sankman, Kemal Aygun, Zhiguo Qian, Ashish Dhall, Jonathan Rosch, Debendra Mallik, and Islam Salama 24 Interconnection Technology Innovations in 2.5D Integrated Electronic Systems 501; Paragkumar A. Thadesar, Paul K. Jo, and Muhannad S. Bakir References 515 Index 521
• Edition: 1st
• Publisher Details: Hoboken : Wiley-IEEE Press
• Publication Date: 2019
• Extent: 1 online resource
• Subjects: 621.395; Chip scale packaging; Integrated circuits -- Wafer-scale integration
• Languages: English
• ISBNs: 9781119313984
• Related ISBNs: 9781119313977
• Notes: Note: Includes bibliographical references and index.; Note: Description based on CIP data; resource not viewed.
• Access Rights: Legal Deposit; Only available on premises controlled by the deposit library and to one user at any one time; The Legal Deposit Libraries (Non-Print Works) Regulations (UK).
• Access Usage: Restricted: Printing from this resource is governed by The Legal Deposit Libraries (Non-Print Works) Regulations (UK) and UK copyright law currently in force.