Learning from VLSI Design Experience. ([2019])

• Record Type: Book
• Further Information: Note: Weng Fook Lee.
• Authors: Lee, Weng Fook
• Contents: Intro; Dedication; Preface; Trademarks; Acknowledgment; Contents; List of Figures; List of Tables; List of Examples; Chapter 1: Introduction; Chapter 2: Design Methodology and Flow; Analog/Custom Design Flow; Digital Design Flow (Fig. 2.7); Synthesis; Standard Cell Library; Design Constraints; Input Delay; Output Delay; Path Delay; Clock Specification; Multicycle Path; False Path; Synthesis Optimizations to Improve Timing; Importance of Clock in Backend; Floor Plan; Clock Tree Synthesis; Chapter 3: Multiple Clock Design; Mean Time Between Failure; Synchronizer Receiving Clock Faster than Transmitting ClockTransmitting Clock Faster than Receiving Clock; Reset; Chapter 4: Latch Inference; If-Else Statement; Case Statement; Chapter 5: Design for Test; Scan Chain; Before Scan; After Scan; Automatic Test Pattern Generation (ATPG); Test Compression; Scan Chain Crossing Different Clock Domains During Shift Phase of ATPG; Scan Chain for Design with Different Power Domains; Capture Phase of ATPG for Multiple Clock Design; Logic Built in Self-Test; How Does Logic BIST Work; Implementation of Logic BIST; Memory BIST; Chapter 6: Signed Verilog Mixing Signed and UnsignedMultiplication and Division of Signed and Unsigned Values; Unsigned Shifting in Verilog; Signed Shifting in Verilog; Rounding Down Due to Signed Shift Right; Simulating RTL Using Signed and Unsigned; Chapter 7: State Machine; RTL Verilog for a State Machine; RTL Coding Style for State Machine Using Two Always Processes; Different RTL Coding Styles for State Machine; When to Use One-Hot, Gray, or Binary Encoding; Blocking Statements; Non-blocking Statements; Rule of Thumb when Using Non-blocking Statement and Blocking Statement; Chapter 8: RTL Coding Guideline ContentionSensitivity List; Level-Sensitive and Edge-Sensitive RTL; Edge-Sensitive RTL Verilog Code; Level-Sensitive RTL Verilog Code; Mixing Level-Sensitive and Edge-Sensitive Verilog Code; Input, Output, and Bidirectional Ports in RTL; Blocking and Non-blocking Statement; Inferred Latch; Signed and Unsigned; Logic between Blocks; Register Output of Blocks; Naming Convention; Chapter 9: Code Coverage; Flow for Code Coverage; Types of Code Coverage; Simulation with Code Coverage; Enhancing Testbench to Increase Code Coverage; References; Index
• Publisher Details: Cham, Switzerland : Springer
• Publication Date: 2019
• Copyright Date: 2019
• Extent: 1 online resource
• Subjects: 621.395; Integrated circuits -- Very large scale integration -- Design; TECHNOLOGY & ENGINEERING / Mechanical; Integrated circuits -- Very large scale integration -- Design; Electronic books
• Languages: English
• ISBNs: 9783030032388; 3030032388
• Related ISBNs: 9783030032371; 303003237X
• Notes: Note: Includes bibliographical references and index.; Note: Online resource; title from PDF title page (EBSCO, viewed December 24, 2018).
• Access Rights: Legal Deposit; Only available on premises controlled by the deposit library and to one user at any one time; The Legal Deposit Libraries (Non-Print Works) Regulations (UK).
• Access Usage: Restricted: Printing from this resource is governed by The Legal Deposit Libraries (Non-Print Works) Regulations (UK) and UK copyright law currently in force.