Flip-flop design in nanometer CMOS : from high speed to low energy /: from high speed to low energy. ([2014])

• Record Type: Book
• Further Information: Note: Massimo Alioto, Elio Consoli, Gaetano Palumbo.
• Authors: Alioto, Massimo; Consoli, Elio; Palumbo, Gaetano
• Contents: Preface; Contents; 1 The Logical Effort Method; 1.1An RC Model for the Delay of Logic Gates; 1.2The Logical Effort Model; 1.3Limitations of the Original Logical Effort Model; 1.4Basic Estimation of Logical Effort Parameters; 1.5Accurate Estimation of Parameters g and p; 1.5.1 Estimation of the Capacitance at Internal Nodes; 1.5.2 Elmore Delay; 1.5.3 Parameter Calibration; 1.5.4 Non-step Input; 1.6Multistage Logic Networks and Delay Minimization; 1.6.1 Path Parameters; 1.6.2 Optimized Design; 1.7Optimum Number of Stages; 1.8Extension of the Model to Non-static Gates. 1.8.1 Dynamic and Domino Gates with Keeper1.8.2 Logic with Transmission Gates and Pass-transistors; 1.9Nonlinearities and Need for Iterative Procedures; Appendix: Derivation of Logical Effort with a Transistor Current Source Model; 2 Design in the Energy-Delay Space; 2.1Energy Modeling; 2.2Energy-Delay Space Analysis and Hardware-Intensity; 2.2.1 The Energy-Efficient Curve; 2.2.2 Energy-Delay Metrics and Hardware Intensity; 2.2.3 Voltage Intensity and Generalization of the Sensitivity Criterion; 2.3Energy-Efficient Design of Digital Circuits; 2.3.1 The Role of the Input Capacitance. 2.3.2 Derivation of Design Space Bounds2.3.3 Simulation-Based Optimization of Small-Sized Circuits; 2.3.4 Nonlinear and Convex Optimization of Large Size Circuits; 2.4Design of Energy-Efficient Pipelined Systems; 2.4.1 Zyuban and Strenski's Hardware-Voltage Intensity Criteria; 2.4.2 Practical Guidelines to Design Energy-Efficient Pipelines; A.1. Appendix: Convex Optimization; 3 Clocked Storage Elements; 3.1 ... Clocking in Synchronous Digital Systems; 3.2 ... Features of the Clock Signal; 3.3 ... Clocked Storage Elements: Latches, Master -- Slave Flip-Flops and Pulsed Topologies. 3.4 ... Timing Parameters of Clocked Storage Elements3.4.1 Setup Time and Hold Time; 3.4.2 The Data Race-Through Issue; 3.4.3 Differences Between Master -- Slave and Pulsed FFs; 3.4.4 Latches; 3.5 ... Clock Uncertainties Absorption and Time Borrowing; 3.6 ... Energy Consumption in Flip-Flops; 3.6.1 Dynamic Energy Dissipation and Techniques for Its Reduction; 3.6.2 Glitches, Short-Circuit and Static Energy Dissipation; 3.7 ... Differential and Dual Edge-Triggered Topologies; 4 Flip-Flop Optimized Design; 4.1 ... A Comprehensive Design Approach; 4.2 ... Definition of Independent Design Variables: Step 1. 4.2.1 A Single Path4.2.2 Two Different Re-converging Paths; 4.2.3 A Bifurcating Path; 4.2.4 Other Cases; 4.3 ... Sizing of Dependent Design Variables: Step 2; 4.3.1 Clocked Precharge Transistors; 4.3.2 Keepers and Noise Immunity; 4.3.3 Feedback Paths; 4.3.4 Pulse Generators; 4.3.4.1 NAND Design; 4.3.4.2 Inverters Chain Design; 4.3.4.3 Different Pulse Generator Topologies; 4.3.5 IDVs and DDVs in SDFF First Stage; 4.4 ... Estimation of Design Space (IDVs) Bounds: Step 3; 4.5 ... Extrapolation of the Energy-Efficient Curve: Step 4; 4.6 ... A Complete Design Example: The SDFF as Case of Study.
• Publisher Details: Cham : Springer
• Publication Date: 2014
• Copyright Date: 2015
• Extent: 1 online resource (xv, 260 pages), illustrations (some color)
• Subjects: 621.3815; Engineering; Metal oxide semiconductors, Complementary -- Design and construction; Flip chip technology; Integrated circuits -- Very large scale integration -- Design and construction; TECHNOLOGY & ENGINEERING -- Mechanical; Flip chip technology; Integrated circuits -- Very large scale integration -- Design and construction; Metal oxide semiconductors, Complementary -- Design and construction; Electrical & Computer Engineering; Engineering & Applied Sciences; Electrical Engineering; Technology & Engineering -- Electronics -- Circuits -- General; Computers -- Systems Architecture -- General; Technology & Engineering -- Nanotechnology & MEMS; Circuits & components; Computer architecture & logic design; Precision instruments manufacture; Systems engineering; Computer science; Electronic books
• Languages: English
• ISBNs: 9783319019970; 3319019961; 9783319019963
• Related ISBNs: 331901997X; 9783319019963
• Notes: Note: Includes bibliographical references and index.; Note: Online resource; title from PDF title page (SpringerLink, viewed October 30, 2014).
• Access Rights: Legal Deposit; Only available on premises controlled by the deposit library and to one user at any one time; The Legal Deposit Libraries (Non-Print Works) Regulations (UK).
• Access Usage: Restricted: Printing from this resource is governed by The Legal Deposit Libraries (Non-Print Works) Regulations (UK) and UK copyright law currently in force.