Design of cost-efficient interconnect processing units : Spidergon STNoC /: Spidergon STNoC. (©2009)
- Record Type:
- Book
- Title:
- Design of cost-efficient interconnect processing units : Spidergon STNoC /: Spidergon STNoC. (©2009)
- Main Title:
- Design of cost-efficient interconnect processing units : Spidergon STNoC
- Further Information:
- Note: Marcello Coppola [and others].
- Other Names:
- Coppola, Marcello
- Contents:
- 1. Towards multicores : technology and software complexity -- 2. On-chip bus vs. network-on-chip -- 3. NoC topology -- 4. The Spidergon STNoC -- 5. SoC and NoC design methodology and tools -- 6. Conclusions and future work -- References -- Index.
- Publisher Details:
- Boca Raton : CRC Press
- Publication Date:
- 2009
- Copyright Date:
- 2009
- Extent:
- 1 online resource (xxi, 265 pages), illustrations
- Subjects:
- 004.1
Networks on a chip
Microprocessors
COMPUTERS -- Hardware -- Mainframes & Minicomputers
Microprocessors
Networks on a chip
Mikroprocessorer
Electronic books - Languages:
- English
- ISBNs:
- 9781420044720
1420044729
1420044710
9781420044713
1281863149
9781281863140 - Notes:
- Note: Includes bibliographical references (pages 235-261) and index.
Note: Print version record. - Access Rights:
- Legal Deposit; Only available on premises controlled by the deposit library and to one user at any one time; The Legal Deposit Libraries (Non-Print Works) Regulations (UK).
- Access Usage:
- Restricted: Printing from this resource is governed by The Legal Deposit Libraries (Non-Print Works) Regulations (UK) and UK copyright law currently in force.
- View Content:
- Available online (eLD content is only available in our Reading Rooms) ↗
- Physical Locations:
- British Library HMNTS - ELD.DS.149539
- Ingest File:
- 01_098.xml