1. Controlled delay‐through dynamic logic: leakage‐tolerant high‐speed dynamic logic. Issue 23 (1st November 2015) Authors: Dev, A.; Sharma, R.K Journal: Electronics letters Issue: Volume 51:Issue 23(2015) Page Start: 1856 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗