Controlled delay‐through dynamic logic: leakage‐tolerant high‐speed dynamic logic. Issue 23 (1st November 2015)

• Record Type: Journal Article
• Authors: Dev, A.; Sharma, R.K
• Is Part Of: Electronics letters. Volume 51:Issue 23(2015)
• Page Start: 1856
• Page End: 1857
• Publication Date: 2015-11-01
• Subjects: leakage currents -- logic circuits -- clocks -- delay circuits -- logic simulation; size 180 nm -- power delay product -- delayed clock mechanism -- control block -- leakage current -- propagation delay -- parallel‐type configuration -- CDTDL circuit -- power consumption -- leakage‐tolerant high‐speed dynamic logic -- controlled delay‐through dynamic logic; Electronics -- Periodicals; 621.381
• DOI: 10.1049/el.2015.0952
• Languages: English
• ISSNs: 0013-5194

Abstract

Abstract : A new model for dynamic logic is proposed with low power consumption and leakage without the degradation of speed. This logic works perfectly with cascaded and differential style without inverters. Controlled delay‐through dynamic logic (CDTDL) is comparatively faster than other dynamic logics because of the parallel‐type configuration with clock and inputs. CDTDL‐based circuits can perform better in high‐frequency operations due to lower propagation delay and dynamic power consumption at the cost of area. The proposed technique can avoid the chance of leakage current with the help of a control block and a delayed clock mechanism. The simulation results show that the new dynamic logic using 180 nm technology yields a minimum 49.7% improvement in power delay product compared with its predecessors such as conventional domino and current comparison‐based domino for standard circuits.