1. Analysis of the reconfiguration latency and energy overheads for a Xilinx Virtex‐5 field‐programmable gate array. Issue 4 (15th March 2018) Authors: Olivito, Javier; Serrano, Felipe; Clemente, Juan Antonio; Mecha, Hortensia; Resano, Javier Journal: IET computers & digital techniques Issue: Volume 12:Issue 4(2018) Page Start: 150 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗