Author/Creator: Zhou, Xichuan - British Library Electronic Legal Deposit Catalogue-Journal Issues and Articles Search Results

Author/Creator Zhou, Xichuan

1. A novel low specific on-resistance double-gate LDMOS with multiple buried p-layers in the drift region based on the Silicon-On-Insulator substrate. (January 2016)

Authors:: Chen, Yinhui; Hu, Shengdong; Cheng, Kun; Jiang, YuYu; Luo, Jun; Wang, Jian'an; Tang, Fang; Zhou, Xichuan; Zhou, Jianlin; Gan, Ping
Journal:: Superlattices and microstructures
Issue:: Volume 89(2016)
Page Start:: 59
Record Type:: Journal Article
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2. A novel trench SOI LDMOS with a dual floating vertical field plate. (September 2017)

Authors:: Cheng, Kun; Hu, Shengdong; Lei, Jianmei; Yuan, Qi; Jiang, Yuyu; Huang, Ye; Yang, Dong; Lin, Zhi; Zhou, Xichuan; Tang, Fang
Journal:: Superlattices and microstructures
Issue:: Volume 109(2017)
Page Start:: 134
Record Type:: Journal Article
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3. An ultra-low specific on-resistance double-gate trench SOI LDMOS with P/N pillars. (December 2017)

Authors:: Yang, Dong; Hu, Shengdong; Lei, Jianmei; Huang, Ye; Yuan, Qi; Jiang, Yuyu; Guo, Jingwei; Cheng, Kun; Lin, Zhi; Zhou, Xichuan; Tang, Fang
Journal:: Superlattices and microstructures
Issue:: Volume 112(2017)
Page Start:: 269
Record Type:: Journal Article
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4. Deep Learning on Edge Computing Devices : Design Challenges of Algorithm and Architecture /: Design Challenges of Algorithm and Architecture. (2022)

Authors:: Zhou, Xichuan; Liu, Haijun; Shi, Cong; Liu, Ji
Record Type:: Book
Extent:: 1 online resource (198 pages)
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5. Improving breakdown, conductive, and thermal performances for SOI high voltage LDMOS using a partial compound buried layer. (March 2016)

Authors:: Hu, Shengdong; Luo, Jun; Jiang, YuYu; Cheng, Kun; Chen, Yinhui; Jin, Jingjing; Wang, Jian'an; Zhou, Jianlin; Tang, Fang; Zhou, Xichuan; Gan, Ping
Journal:: Solid-state electronics
Issue:: Volume 117(2016)
Page Start:: 146
Record Type:: Journal Article
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6. Improving breakdown, conductive, and thermal performances for SOI high voltage LDMOS using a partial compound buried layer. (March 2016)

Authors:: Hu, Shengdong; Luo, Jun; Jiang, YuYu; Cheng, Kun; Chen, Yinhui; Jin, Jingjing; Wang, Jian'an; Zhou, Jianlin; Tang, Fang; Zhou, Xichuan; Gan, Ping
Journal:: Solid-state electronics
Issue:: Volume 117(2016)
Page Start:: 146
Record Type:: Journal Article
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7. Ultra-Low Specific On-Resistance Trench SOI LDMOS with a Floating Lateral Field Plate. Issue 4 (4th July 2018)

Authors:: Yang, Dong; Hu, Shengdong; Huang, Ye; Jiang, Yuyu; Cheng, Kun; Yuan, Qi; Lei, Jianmei; Lin, Zhi; Zhou, Xichuan; Tang, Fang
Journal:: IETE technical review
Issue:: Volume 35:Issue 4(2018)
Page Start:: 342
Record Type:: Journal Article
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