1. Design techniques for decision feedback equalisation of multi‐giga‐bit‐per‐second serial data links: a state‐of‐the‐art review. Issue 2 (1st March 2014) Authors: Yuan, Fei; AL‐Taee, Alaa R.; Ye, Andy; Sadr, Saman Journal: IET circuits, devices & systems Issue: Volume 8:Issue 2(2014) Page Start: 118 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
2. Minimum jitter‐based adaptive decision feedback equaliser for giga‐bit‐per‐second serial links. Issue 1 (14th January 2015) Authors: Al‐Taee, Alaa Rahman; Yuan, Fei; Ye, Andy Journal: Journal of engineering Issue: Volume 2015:Issue 1(2015) Page Start: 25 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
3. Static power model for CMOS and FPGA circuits. Issue 4 (23rd March 2021) Authors: Razzaq, Anas; Ye, Andy Journal: IET computers & digital techniques Issue: Volume 15:Issue 4(2021) Page Start: 263 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗