Static power model for CMOS and FPGA circuits. Issue 4 (23rd March 2021)

• Record Type: Journal Article
• Authors: Razzaq, Anas; Ye, Andy
• Is Part Of: IET computers & digital techniques. Volume 15:Issue 4(2021)
• Page Start: 263
• Page End: 278
• Publication Date: 2021-03-23
• Subjects: Computers -- Periodicals; Digital electronics -- Periodicals; Computer engineering -- Periodicals; Computer architecture -- Periodicals; Computer organization -- Periodicals; 621.39
• DOI: 10.1049/cdt2.12021
• Languages: English
• ISSNs: 1751-8601

Abstract

Abstract: In Ultra‐Low‐Power (ULP) applications, power consumption is a key parameter for process independent architectural level design decisions. Traditionally, time‐consuming Spice simulations are used to measure the static power consumption. Herein, a technology‐independent static power estimation model is presented, which can estimate static power with reasonable accuracy in much less time. It is shown that active area only is not a good indicator for static power consumption, hence in this model, the effects of transistor sizing, transistor stacking, gate boosting and voltage change are considered. The procedure to apply this model to processors and FPGAs is demonstrated. Across different process technologies, compared to traditional spice simulation, this model can estimate the static power consumption of processor with an error of 1%–4%, while static power consumption of an FPGA system with an error of 1%–15%.