1. Extraction and modeling of layout-dependent MOSFET gate-to-source/drain fringing capacitance in 40 nm technology. (September 2015) Authors: Sun, Lijie; Shang, Ganbing; Liu, Linlin; Cheng, Jia; Guo, Ao; Ren, Zheng; Hu, Shaojian; Chen, Shoumian; Zhao, Yuhang; Chan, Mansun; Zhang, Long; Li, Xiaojin; Shi, Yanling Journal: Solid-state electronics Issue: Volume 111(2015) Page Start: 118 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
2. Extraction and modeling of layout-dependent MOSFET gate-to-source/drain fringing capacitance in 40 nm technology. (September 2015) Authors: Sun, Lijie; Shang, Ganbing; Liu, Linlin; Cheng, Jia; Guo, Ao; Ren, Zheng; Hu, Shaojian; Chen, Shoumian; Zhao, Yuhang; Chan, Mansun; Zhang, Long; Li, Xiaojin; Shi, Yanling Journal: Solid-state electronics Issue: Volume 111(2015) Page Start: 118 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗