1. Benchmarks of a III-V TFET technology platform against the 10-nm CMOS FinFET technology node considering basic arithmetic circuits. (February 2017) Authors: Strangio, S.; Palestri, P.; Lanuzza, M.; Esseni, D.; Crupi, F.; Selmi, L. Journal: Solid-state electronics Issue: Volume 128(2017) Page Start: 37 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
2. Digital and analog TFET circuits: Design and benchmark. (August 2018) Authors: Strangio, S.; Settino, F.; Palestri, P.; Lanuzza, M.; Crupi, F.; Esseni, D.; Selmi, L. Journal: Solid-state electronics Issue: Volume 146(2018) Page Start: 50 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
3. On the interpretation of MOS impedance data in both series and parallel circuit topologies. (November 2021) Authors: Caruso, E.; Lin, J.; Monaghan, S.; Cherkaoui, K.; Floyd, L.; Gity, F.; Palestri, P.; Esseni, D.; Selmi, L.; Hurley, P.K. Journal: Solid-state electronics Issue: Volume 185(2021) Page Start: Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
4. Optimization of GaAs/AlGaAs staircase avalanche photodiodes accounting for both electron and hole impact ionization. (June 2020) Authors: Pilotto, A.; Nichetti, C.; Palestri, P.; Selmi, L.; Antonelli, M.; Arfelli, F.; Biasiol, G.; Cautero, G.; Driussi, F.; Esseni, D.; Menk, R.H.; Steinhartova, T. Journal: Solid-state electronics Issue: Volume 168(2020) Page Start: Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗