1. A comparative mismatch study of the 20 nm Gate-Last and 28 nm Gate-First bulk CMOS technologies. (June 2015) Authors: Rahhal, Lama; Bajolet, Aurelie; Manceau, Jean-Philippe; Rosa, Julien; Ricq, Stephane; Lassere, Sebastien; Ghibaudo, Gerard Journal: Solid-state electronics Issue: Volume 108(2015) Page Start: 53 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗