1. Design considerations and optimisation of clock circuit for ultra-low power sub-threshold applications. Issue 3 (3rd July 2018) Authors: Walunj, R. A.; Pable, S. D.; Kharate, G. K. Journal: Australian journal of electrical & electronics engineering Issue: Volume 15:Issue 3(2018) Page Start: 98 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
2. Optimization and Characterization of CMOS for Ultra Low Power Applications. (22nd December 2015) Authors: Kafeel, Mohd. Ajmal; Pable, S. D.; Hasan, Mohd.; Alam, M. Shah Other Names: Jha Niraj K. Academic Editor. Journal: Journal of nanotechnology Issue: Volume 2015(2015) Page Start: Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
3. Robustness Comparison of Emerging Devices for Portable Applications. (28th February 2012) Authors: Pable, S. D.; Kafeel, Mohd. Ajmal; Kureshi, A. K.; Hasan, Mohd. Other Names: Brosseau Christian Academic Editor. Journal: Journal of nanomaterials Issue: Volume 2012(2012) Page Start: Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
4. Ultra low power DG FinFET based voltage controlled oscillator circuits. Issue 1 (2nd January 2019) Authors: Walunj, R. A.; Pable, S. D.; Kharate, G. K. Journal: International journal of electronics Issue: Volume 106:Issue 1(2019) Page Start: 134 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗