Design considerations and optimisation of clock circuit for ultra-low power sub-threshold applications. Issue 3 (3rd July 2018)

• Record Type: Journal Article
• Authors: Walunj, R. A.; Pable, S. D.; Kharate, G. K.
• Is Part Of: Australian journal of electrical & electronics engineering. Volume 15:Issue 3(2018)
• Page Start: 98
• Page End: 117
• Publication Date: 2018-07-03
• Subjects: sub-threshold -- voltage controlled oscillator (VCO) -- current starved VCO (CSVCO) -- PVT (processvoltage and temperature) variations -- Monte Carlo simulations; Electrical engineering -- Periodicals; Electronics -- Periodicals; Periodicals; 621.305
• DOI: 10.1080/1448837X.2018.1527101
• Languages: English
• ISSNs: 1448-837X

Abstract

ABSTRACT: Clock system plays a vital role in governing the reliability, power consumption and performance of synchronous system. In today's era of portable electronics, power consumption has emerged as a forefront design metrics. Sub-threshold operation of devices is an excellent option to have an ultra-low power system. However, degraded performance and exacerbated variability are the major concerns of the sub-threshold circuits. Furthermore, as contradictory to the conventional super threshold circuits, the device resistance for the sub-threshold circuits is quite high compared to the interconnect resistance. This paper therefore, explores the design constraints for sub-threshold clock system. It further explores the suitability of buffered and un-buffered clock system in deep sub-threshold regime. The impact of supply voltage scaling and 3σ/µ variability for clock system is investigated in this work. An attempt to improve the slew of the clock system with un-buffered tree is made by redesigning the tapered H tree which exhibits better slew and robustness in sub-threshold regime.