1. Experimental demonstration of high-gain CMOS inverter operation at low Vdd down to 0.5 V consisting of WSe2 n/p FETs. (1st May 2022) Authors: Kawanago, Takamasa; Matsuzaki, Takahiro; Kajikawa, Ryosuke; Muneta, Iriya; Hoshii, Takuya; Kakushima, Kuniyuki; Tsutsui, Kazuo; Wakabayashi, Hitoshi Journal: Japanese journal of applied physics Issue: Volume 61:Number SC(2022) Page Start: Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
2. Experimental demonstration of high-gain CMOS inverter operation at low Vdd down to 0.5 V consisting of WSe2 n/p FETs. (1st May 2022) Authors: Kawanago, Takamasa; Matsuzaki, Takahiro; Kajikawa, Ryosuke; Muneta, Iriya; Hoshii, Takuya; Kakushima, Kuniyuki; Tsutsui, Kazuo; Wakabayashi, Hitoshi Journal: Japanese journal of applied physics Issue: Volume 61:Number SC(2022) Page Start: Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
3. Experimental demonstration of high-gain CMOS inverter operation at low Vdd down to 0.5 V consisting of WSe2 n/p FETs. (7th February 2022) Authors: Kawanago, Takamasa; Matsuzaki, Takahiro; Kajikawa, Ryosuke; Muneta, Iriya; Hoshii, Takuya; Kakushima, Kuniyuki; Tsutsui, Kazuo; Wakabayashi, Hitoshi Journal: Japanese journal of applied physics Issue: Volume 61:Number SC(2022) Page Start: Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗