Experimental demonstration of high-gain CMOS inverter operation at low Vdd down to 0.5 V consisting of WSe2 n/p FETs. (7th February 2022)

• Record Type: Journal Article
• Authors: Kawanago, Takamasa; Matsuzaki, Takahiro; Kajikawa, Ryosuke; Muneta, Iriya; Hoshii, Takuya; Kakushima, Kuniyuki; Tsutsui, Kazuo; Wakabayashi, Hitoshi
• Is Part Of: Japanese journal of applied physics. Volume 61:Number SC(2022)
• Publication Date: 2022-02-07
• Subjects: WSe2 FET -- TMDC -- CMOS Inverter; Physics -- Periodicals; 621.05
• DOI: 10.35848/1347-4065/ac3a8e
• Languages: English
• ISSNs: 0021-4922

Abstract

Abstract: In this paper, we report on the device concepts for high-gain operation of a tungsten diselenide (WSe2 ) complementary metal-oxide-semiconductor (CMOS) inverter at a low power supply voltage ( V dd ), which was realized by developing a doping technique and gate stack technology. A spin-coating with a fluoropolymer and poly(vinyl alcohol) (PVA) results in the doping of both electrons and holes to WSe2 . A hybrid self-assembled monolayer/aluminum oxide (AlO x ) gate dielectric is viable for achieving high gate capacitance and superior interfacial properties. By developing the doping technique and gate stack technology, we experimentally realized a high gain of 9 at V dd of 0.5 V in the WSe2 CMOS inverter. This study paves the way for the research and development of transition metal dichalcogenides-based devices and circuits.