1. (Invited) Factors Impacting Threshold Voltage in Advanced CMOS Integration: Gate Last (FINFET) vs. Gate First (FDSOI). (8th September 2015) Authors: Triyoso, Dina; Carter, Rick; Kluth, Jon; Luning, Scott; Child, Amy; Wahl, Jeremy; Mulfinger, Bob; Punchihewa, Kasun; Kumar, Anil; Kang, Laegu; Sporer, Ryan; Chen, Xiaobo; Straub, Sherry; Bohra, Girish; Patil, Suraj; Zhang, Xing; Chen, Alex; Togo, Mitsuhiro; Pal, Rohit Journal: ECS transactions Issue: Volume 69:Number 5(2015) Page Start: 103 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
2. (Invited)Extending Advanced CMOS Scaling with SiGe Channel Materials. (9th April 2018) Authors: Carter, Rick J; Sporer, Ryan; McArdle, Timothy J; Mulfinger, George Robert; Holt, Judson Robert; Beasor, Scott; Child, Amy; Fronheiser, Jody; Wahl, Jeremy A; Geisler, Holm; Kluth, George J; Triyoso, Dina H; Punchihewa, Kasun; Rana, Uzma; Vanamurthy, Laks; Sohn, D K Journal: ECS transactions Issue: Volume 85:Number 6(2018) Page Start: 3 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
3. Buried SiGe as a performance booster in n-channel FDSOI MOSFETs. (December 2019) Authors: Clifton, Paul; Goebel, Andreas; Mulfinger, Robert; Child, Amy; Straub, Sherry; Sporer, Ryan; Carter, Rick; Kluth, Jon; Schaeffer, Jamie; Nguyen, Bich-Yen; Chabanne, Guillaume; Daval, Nicolas; Schwarzenbach, Walter; Hemkar, Manish; Chu, Schubert; Moffatt, Steve Journal: Solid-state electronics Issue: Volume 162(2019) Page Start: Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗