1. (Invited) Factors Impacting Threshold Voltage in Advanced CMOS Integration: Gate Last (FINFET) vs. Gate First (FDSOI). (8th September 2015) Authors: Triyoso, Dina; Carter, Rick; Kluth, Jon; Luning, Scott; Child, Amy; Wahl, Jeremy; Mulfinger, Bob; Punchihewa, Kasun; Kumar, Anil; Kang, Laegu; Sporer, Ryan; Chen, Xiaobo; Straub, Sherry; Bohra, Girish; Patil, Suraj; Zhang, Xing; Chen, Alex; Togo, Mitsuhiro; Pal, Rohit Journal: ECS transactions Issue: Volume 69:Number 5(2015) Page Start: 103 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
2. Metal Flake Defect and Its Formation Mechanism during Replacement Metal Gate CMP Process. (1st January 2016) Authors: Kim, Hong Jin; Govindarajulu, Venugopal; Bohra, Girish; Wang, Huey-Ming; Koli, Dinesh Journal: ECS journal of solid state science and technology Issue: Volume 5:Number 10(2016) Page Start: P637 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
3. Metal Flake Defect and Its Formation Mechanism during Replacement Metal Gate CMP Process. (5th October 2016) Authors: Kim, Hong Jin; Govindarajulu, Venugopal; Bohra, Girish; Wang, Huey-Ming; Koli, Dinesh Journal: ECS journal of solid state science and technology Issue: Volume 5:Number 10(2016) Page Start: P637 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗