1. Benefits of using arrays of vertical nanowire FETs in integrated circuits to mitigate variability. (12th November 2021) Authors: del Moral, A; Amat, E; Bausells, J; Perez-Murano, F Journal: Semiconductor science and technology Issue: Volume 36:Number 12(2021) Page Start: Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
2. CMOS compatible manufacturing of a hybrid SET-FET circuit. (1st December 2022) Authors: del Moral, A; Amat, E; Engelmann, H-J; Pourteau, M-L; Rademaker, G; Quirion, D; Torres-Herrero, N; Rommel, M; Heinig, K-H; von Borany, J; Tiron, R; Bausells, J; Perez-Murano, F Journal: Semiconductor science and technology Issue: Volume 37:Number 12(2022) Page Start: Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗