1. A Pattern Recognition Mezzanine based on Associative Memory and FPGA technology for Level 1 Track Triggers for the HL-LHC upgrade. (22nd February 2016) Authors: Magalotti, D.; Alunni, L.; Biesuz, N.; Bilei, G.M.; Citraro, S.; Crescioli, F.; Fanò, L.; Fedi, G.; Magazzù, G.; Servoli, L.; Storchi, L.; Palla, F.; Placidi, P.; Rossi, E.; Spiezia, A. Journal: Journal of instrumentation Issue: Volume 11:Number 2(2016:Feb.) Page Start: C02063 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗