A Pattern Recognition Mezzanine based on Associative Memory and FPGA technology for Level 1 Track Triggers for the HL-LHC upgrade. (22nd February 2016)

• Record Type: Journal Article
• Authors: Magalotti, D.; Alunni, L.; Biesuz, N.; Bilei, G.M.; Citraro, S.; Crescioli, F.; Fanò, L.; Fedi, G.; Magazzù, G.; Servoli, L.; Storchi, L.; Palla, F.; Placidi, P.; Rossi, E.; Spiezia, A.
• Is Part Of: Journal of instrumentation. Volume 11:Number 2(2016:Feb.)
• Page Start: C02063
• Page End: C02063
• Publication Date: 2016-02-22
• Subjects: Digital electronic circuits -- Front-end electronics for detector readout -- Trigger concepts and systems (hardware and software); Scientific apparatus and instruments -- Periodicals; 502.84
• DOI: 10.1088/1748-0221/11/02/C02063
• Languages: English
• ISSNs: 1748-0221

Abstract

Abstract: The increment of luminosity at HL-LHC will require the introduction of tracker information at Level-1 trigger system for the experiments in order to maintain an acceptable trigger rate for selecting interesting events despite the one order of increased magnitude in the minimum bias interactions. In order to extract the track information in the required latency ( ∼ 5–10 μ s depending on the experiment), a dedicated hardware processor needs to be used. We here propose a prototype system (Pattern Recognition Mezzanine) as core of pattern recognition and track fitting for HL-LHC experiments, combining the power of both Associative Memory custom ASIC and modern Field Programmable Gate Array (FPGA) devices.