1. Fabrication and electrical characterizations of SGOI tunnel FETs with gate length down to 50 nm. (January 2016) Authors: Le Royer, C.; Villalon, A.; Hutin, L.; Martinie, S.; Nguyen, P.; Barraud, S.; Glowacki, F.; Allain, F.; Bernier, N.; Cristoloveanu, S.; Vinet, M. Journal: Solid-state electronics Issue: Volume 115 Part B(2016) Page Start: 167 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
2. New insights on SOI Tunnel FETs with low-temperature process flow for CoolCube™ integration. (June 2018) Authors: Diaz Llorente, C.; Le Royer, C.; Batude, P.; Fenouillet-Beranger, C.; Martinie, S.; Lu, C.-M.V.; Allain, F.; Colinge, J.-P.; Cristoloveanu, S.; Ghibaudo, G.; Vinet, M. Journal: Solid-state electronics Issue: Volume 144(2018) Page Start: 78 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗