A low-power 1 Gb/s line driver with configurable pre-emphasis for lossy transmission lines. (1st April 2023)

• Record Type: Journal Article
• Authors: St. John, N.; Mandal, S.; Miryala, S.; Maj, P.; Deptuch, G.W.; Raguzin, E.; Rescia, S.
• Is Part Of: Journal of instrumentation. Volume 18:Number 4(2023)
• Publication Date: 2023-04-01
• Subjects: Digital electronic circuits -- Digital signal processing (DSP) -- VLSI circuits; Scientific apparatus and instruments -- Periodicals; 502.84
• DOI: 10.1088/1748-0221/18/04/C04009
• Languages: English
• ISSNs: 1748-0221

Abstract

Abstract: A line driver with configurable pre-emphasis is implemented in a 65 nm CMOS process. The driver utilizes a three-tap feed-forward equalization architecture. The relative delays between the taps are selectable in increments of 1/16th of the unit interval via an 8-stage delay-locked loop and digital interpolator. It is also possible to control the output amplitude and source impedance for each tap via a programmable array of eight source-series terminated drivers. The entire design consumes 9 mW from a 1.2 V supply at 1 Gb/s.