Fabrication Technologies for the On‐Chip Integration of 2D Materials. Issue 3 (7th January 2022)

• Record Type: Journal Article
• Authors: Jia, Linnan; Wu, Jiayang; Zhang, Yuning; Qu, Yang; Jia, Baohua; Chen, Zhigang; Moss, David J.
• Is Part Of: Small methods. Volume 6:Issue 3(2022)
• Page Start: n/a
• Page End: n/a
• Publication Date: 2022-01-07
• Subjects: 2D materials -- fabrication techniques -- heterostructures -- integrated devices; Nanotechnology -- Methodology -- Periodicals; Nanotechnology -- Periodicals; Periodicals; 620.5028
• DOI: 10.1002/smtd.202101435
• Languages: English
• ISSNs: 2366-9608

Abstract

Abstract: With compact footprint, low energy consumption, high scalability, and mass producibility, chip‐scale integrated devices are an indispensable part of modern technological change and development. Recent advances in 2D layered materials with their unique structures and distinctive properties have motivated their on‐chip integration, yielding a variety of functional devices with superior performance and new features. To realize integrated devices incorporating 2D materials, it requires a diverse range of device fabrication techniques, which are of fundamental importance to achieve good performance and high reproducibility. This paper reviews the state‐of‐art fabrication techniques for the on‐chip integration of 2D materials. First, an overview of the material properties and on‐chip applications of 2D materials is provided. Second, different approaches used for integrating 2D materials on chips are comprehensively reviewed, which are categorized into material synthesis, on‐chip transfer, film patterning, and property tuning/modification. Third, the methods for integrating 2D van der Waals heterostructures are also discussed and summarized. Finally, the current challenges and future perspectives are highlighted. Abstract : With a compact footprint, low energy consumption, high scalability, mass producibility, and unique structures with distinctive properties, 2D layered materials are revolutionizing chip‐scale integrated devices. This paper reviews state‐of‐art fabrication techniques for the integration of 2D materials, including material synthesis, on‐chip transfer, film patterning, property tuning/modification, 2D van der Waals heterostructures, finishing with current challenges and future perspectives.