Characterization and compact modeling of short channel MOSFETs at cryogenic temperatures. (June 2023) - Huang, Jixiang; Zhang, Yuanke; Chen, Yuefeng; Xu, Jun; Luo, Chao; Guo, Guoping
Abstract: This paper presents an overall characterization, physics-based device analysis, and compact modeling of a commercial 110 nm bulk CMOS technology. I − V measurements and DC parameters extraction are performed on low threshold voltage (low V T H, LVT) and regular V T H (RVT) devices with various geometry dimensions from 300 K to 6 K. Different levels of improvement of subthreshold swing ( S S ), OFF -state current ( I O F F ), and mobility indicates the potential to optimize the performance of circuits at cryogenic temperatures. However, the temperature characteristics of the mobility and series resistance show a great dependence on the channel length of the devices, which complicates the calculation of the ON -state current at cryogenic temperatures. Moreover, V T H roll-off caused by short channel effect (SCE) get worse, which can be attributed to the increased bulk Fermi potential ( ϕ f ). These channel-length-related effects add extra challenges to the design of cryogenic circuits. An optimized compact model based on BSIM4 is proposed to capture the device characteristics at 6 K, which can produce accurate simulation results only through parameter configuration rather than model equation modification and has been applied to the design of cryogenic CMOS circuits. Highlights: The cryogenic characterization of Nexchip 110 nm CMOS technology is presented. Mobility collapse, threshold voltage roll-up and roll-off are investigated at 6 K. A compact model that can precisely describe the devices at 6 K is proposed.