A DTC-based Fractional-N DPLL using probability-density-shaping spur immunity and Q-noise reduction techniques for IoT applications. (May 2023)
- Record Type:
- Journal Article
- Title:
- A DTC-based Fractional-N DPLL using probability-density-shaping spur immunity and Q-noise reduction techniques for IoT applications. (May 2023)
- Main Title:
- A DTC-based Fractional-N DPLL using probability-density-shaping spur immunity and Q-noise reduction techniques for IoT applications
- Authors:
- Jin, Zirui
Shan, Xiaoyu
Hu, Ang
Liu, Dongsheng
Cheng, Xuan
Cui, Jinsong
Zhang, Chengcheng
Lei, Jianming - Abstract:
- Abstract: A Digital-to-Time Converter based (DTC-based) fractional- N digital phase-locked loop (DPLL) using probability-density-shaping (PDS) spur immunity and quantization phase (Q-noise) reduction techniques is presented. PDS-DSM is used to generate a loop spur immunity control code for DTC. A diff type dither is proposed to further suppress the fractional spur. The loop nonlinearity will not cause fractional spurs if certain conditions are obeyed. Moreover, to reduce the quantization noise, a configurable Phase Interpolator (PI) with 0.125/0.25/0.5/1.0 division step is integrated with a multi-module divider (MMDIV), leading to an 18-dB Q-noise suppression. A reference doubler with duty-cycle correction is adopted to further reduce phase noise. The fractional spurs are greatly mitigated by combining the PDS-DSM and phase interpolator. A DPLL prototype using the aforementioned techniques was designed in a 40-nm standard CMOS process, occupying a 0.99 mm 2 silicon area. At a near-integer- N frequency, i.e., near 2.23 GHz, with PDS turned on and off, the post-layout simulated fractional spur is −59 dBc and −20 dBc, respectively. The RMS jitter of the whole chip is 4.218 ps, corresponding to a figure of merit (FOM) of −220.5 dB.
- Is Part Of:
- Microelectronics journal. Volume 135(2023)
- Journal:
- Microelectronics journal
- Issue:
- Volume 135(2023)
- Issue Display:
- Volume 135, Issue 2023 (2023)
- Year:
- 2023
- Volume:
- 135
- Issue:
- 2023
- Issue Sort Value:
- 2023-0135-2023-0000
- Page Start:
- Page End:
- Publication Date:
- 2023-05
- Subjects:
- Digital phase-locked loop (DPLL) -- Fractional spur -- Phase interpolator (PI) -- Probability density-shaping delta-sigma modulator (PDS-DSM) -- Nonlinearity (NL) -- Reference doubler -- RMS jitter
Microelectronics -- Periodicals
Microélectronique -- Périodiques
Microelectronics
Electronic journals
Journals - contents and abstracts
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621.3805 - Journal URLs:
- http://catalog.hathitrust.org/api/volumes/oclc/5877621.html ↗
http://www.sciencedirect.com/science/journal/00262692 ↗
http://www.intute.ac.uk/sciences/cgi-bin/fullrecord.pl?handle=lesa.1012319367 ↗
http://www.elsevier.com/journals ↗
http://www.elsevier.com/homepage/elecserv.htt ↗ - DOI:
- 10.1016/j.mejo.2023.105753 ↗
- Languages:
- English
- ISSNs:
- 0959-8324
- Deposit Type:
- Legaldeposit
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