Compact size buck converter using small output capacitance with pole-tuning technique. (May 2023) - Lee, Jae-Eun; Cho, Young-Kyun; Kim, Choul-Young
Abstract: This paper presents a compact buck converter using a pole-tuning technique in a 180-nm bulk CMOS process. The proposed pole-tuning technique enables the miniaturization of the output capacitor by reducing the required capacitance and improves the regulation characteristics by optimizing the inductor. The designed converter uses a high-speed switching frequency to reduce the inductor size, and by tuning the poles, the unity-gain bandwidth of the circuit is maintained. The ripple size owing to the reduced size of the capacitor showed a negligible change owing to the equivalent series resistance of the LCR filter. The designed buck converter uses an inductor of 0.1 μH and a capacitor of 0.1 μF. To apply a wide current range and high power efficiency, the converter has a load current range of 50–1000 mA and generates a voltage of 0.6–1.5 V with a source of 1.6–2.4 V. The designed buck converter was fabricated using a 0.18 μm CMOS. It operates at a switching frequency of 30 MHz, and the current ripple is within 15% under full load conditions. The converter exhibited a peak efficiency of 92.2% at 800 mA and conversion efficiency of over 76% over a load range of 50–1000 mA.