A 90 nm area and power efficient Carry Select Adder using 2–1 multiplexer based Excess-1 block. (1st March 2023)

• Record Type: Journal Article
• Authors: Jeevan, B; Bikshalu, K; Sivani, K
• Is Part Of: Engineering research express. Volume 5:Number 1(2023)
• Publication Date: 2023-03-01
• Subjects: digital -- carry select adder -- VLSI -- cadence -- multiplexer; Engineering -- Periodicals; 620.005
• DOI: 10.1088/2631-8695/acc514
• Languages: English
• ISSNs: 2631-8695

Abstract

Abstract: This paper proposes a novel architecture of excess-1 adder-based Carry Select Adder (M2CSA) using single leaf cell i.e., 2–1 Multiplexer. M2CSA is designed using a new type of Excess-1 block. The Excess-1 block is designed in a distinct way using 2–1 multiplexers. The architectures of the proposed carry select adder and its internal excess-1 blocks are completely distinct when compared to existing carry select adders. The proposed 4-, 8-, 16-, 32-, and 64-bit M2CSAs use a 2–1 multiplexer only. The complex gates such as XOR gates are eliminated which exist in existing Carry Select Adders (CaSeAs). A 64-bit M2CSA that utilises one kind of 2-1 Mux cell is clearly decomposed to retain outstanding cell regularity. In previous designs, ripple carry adder blocks are substituted with half adders by limiting carry propagation to a particular degree. By avoiding carry propagation over adder blocks, particularly in 32- and 64-bit adders, the performance of M2CSA is initially increased. For CaSeAs, the area is of primary significance; for M2CSAs, it is also diminished by preserving cell regularity. Verilog HDL is utilised in the design of the M2CSA and current CaSeAs. Using Cadence NCLaunch, all of the designs are functionally tested. At a 90nm technology node, all of the designs are generated and executed using Genus and Innovus tools, respectively. As a comparison to prior designs, the 64-bit M2CSA final ASIC architecture is on average 17% less in terms of space. The comparison and result analysis show that 64-bit M2CSA performs 20% and 19% faster than 64-bit SQCSC in terms of performance and power dissipation, respectively.. The proposed 4-, 8-, 16-, 32-, 64- bit M2CSA exhibits less PDP (Power-Delay Product) ranging from 25%–30% concerning SQCSCs. Similarly, EDP (Energy- Delay Product) values for all the designs are calculated. The improvement in EDP for the 4-, 8-, 16-, 32-, 64- bit M2CSA is 41, 38, 42, 43, and 45 percentages compared to 4-, 8-, 16-, 32-, 64- bit SQCSC respectively. Therefore, the M2CSAs outperform the existing designs in terms of EDP by 38%–45%.