Integrated three-dimensional Hall switch sensor based on independent optimized Hall devices. (May 2023)

• Record Type: Journal Article
• Authors: Guo, Shizhong
• Is Part Of: Microelectronics journal. Volume 135(2023)
• Publication Date: 2023-05
• Subjects: 3D Hall switch sensor -- Hall devices -- Matching -- Independent optimization -- Sensitivity -- Offset -- Time-division multiplexing -- Wake-up and sleep mode; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2023.105756
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: This paper presents an integrated 3D Hall switch sensor with a 100 kHz signal bandwidth, which can detect three-dimensional (3D) magnetic field and output digital signals. 3D magnetic field detection relies on the integration of the horizontal Hall devices (HHD) and vertical Hall devices (VHD), and usually requires the performance of HHD and VHD to match each other. Therefore, an independent optimization method is applied to 3D Hall sensor to realize the matching between HHD and VHD. This method allows the doping concentration and doping profiles of VHD can be designed different from HHD. The simulation results show that the optimized HHD can achieve a voltage sensitivity SV of about 20mV/VT and a residual offset of 20 μV at a 3.3 V supply voltage, while VHD are optimized independently for SV up to 20mV/VT, and the residual offset is less than 100 μV after applying offset cancellation technology. In addition, in order to reduce the power consumption and area of the Hall sensor, the Hall signal processing circuit adopts the time-division multiplexing method to realize the detection of the 3D magnetic field in one working period. During the working period, the circuit uses logic control timing circuit to realize wake-up and sleep mode, which further effectively reduces the overall power consumption of the sensor. The Hall sensor chip has been fabricated in 0.18 μm CMOS technology with an area of 1.46 mm 2 . The measured results show the power consumption of the chip in the Z-axis direction is about 11.88 mW in the wake-up mode and only 49 μW in the sleep mode, at a 3.3 V supply voltage.