A fourth‐order incremental ADC in three‐step. Issue 7 (6th May 2021)

• Record Type: Journal Article
• Authors: Huang, Jia‐Sheng; Kuo, Shih‐Che; Kao, Chia‐Wei; Huang, Yu‐Cheng; Hsu, Che‐Wei; Chen, Chia‐Hung
• Is Part Of: Journal of engineering. Volume 2021:Issue 7(2021)
• Page Start: 394
• Page End: 398
• Publication Date: 2021-05-06
• Subjects: Logic circuits -- A/D and D/A convertors -- CMOS integrated circuits -- A/D and D/A convertors; Engineering -- Periodicals; Engineering; Electronic journals; Periodicals; 620.005
• DOI: 10.1049/tje2.12044
• Languages: English
• ISSNs: 2051-3305

Abstract

Abstract: This letter presents a second‐order incremental ADC (IADC) operated in three steps, which extends the performance of a second‐order IADC close to that of a fourth‐order IADC with only two amplifiers. It performs a second‐order noise‐shaping quantization in the first step operation. Reusing the same hardware, the circuit is reconfigured to perform fine quantization as a first‐order IADC in the second and third step. Within a conversion time of 60 clock periods (oversampling ratio OSR = 60), 35 dB signal‐to‐quantization‐noise ratio is boosted. The proposed topology is very suitable for low‐bandwidth high‐resolution data conversion.