New negative‐grounded capacitance multiplier circuits. (15th November 2022) - Raj, Ajishek
Summary: In this communication, three new negative‐grounded capacitance multiplier (NGCM) circuits employing a single current feedback operational amplifier (CFOA), two resistors, and a grounded capacitor (which is most suitable for parasitic absorption and also IC implementation point of view) are investigated. No matching constraints are required for any of the proposed circuit realizations. Out of the three proposed circuits, multiplication factor of one of the capacitance multiplier can be controlled electronically as the controlling resistor is grounded, which can easily be replaced by a voltage‐controlled resistor (VCR). Error analysis of the proposed NGCMs has been carried out, and the results have been compared with those obtained from ideal analysis. To substantiate the feasibility of the proposed circuits, macro model of CFOA has been used, and the simulations have been performed in Personal Simulation Program with Integrated Circuit Emphasis (PSPICE). Simulation results for frequency analysis, Monte‐Carlo analysis, and temperature analysis have been included for the theoretical justification. Noise analysis and power supply rejection ratio analysis have also been carried out for the proposed circuits. The multiplication factors of the proposed NGCMs have been obtained up to a maximum value of 2001. The impedance and phase of the proposed NGCM structures are insensitive with temperature. The functionality of the proposed structures has also been validated experimentally using commercially available IC AD844‐type CFOA. Abstract : In this communication, three new negative‐grounded capacitance multiplier circuits employing a single current feedback operational amplifier (CFOA), two resistors, and a grounded capacitor are investigated. To substantiate the feasibility of the proposed circuits, macro model of CFOA has been used. Simulation results for frequency analysis, Monte‐Carlo analysis, and temperature analysis have been included for the theoretical justification. Noise analysis and power supply rejection ratio analysis have also been carried out for the proposed circuits.