Cite
HARVARD Citation
Sheikhpur, S. et al. (2021). Strengthened 32‐bit AES implementation: Architectural error correction configuration with a new voting scheme. IET computers & digital techniques. 15 (6), pp. 395-408. [Online].
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Sheikhpur, S. et al. (2021). Strengthened 32‐bit AES implementation: Architectural error correction configuration with a new voting scheme. IET computers & digital techniques. 15 (6), pp. 395-408. [Online].