Automatic diagnosis of single fault in interconnect testing of SRAM‐based FPGA. Issue 5 (4th April 2021)

• Record Type: Journal Article
• Authors: Nirmalraj, T.; Radhakrishnan, S.; Pandiyan, S.K.
• Is Part Of: IET computers & digital techniques. Volume 15:Issue 5(2021)
• Page Start: 362
• Page End: 371
• Publication Date: 2021-04-04
• Subjects: Computers -- Periodicals; Digital electronics -- Periodicals; Computer engineering -- Periodicals; Computer architecture -- Periodicals; Computer organization -- Periodicals; 621.39
• DOI: 10.1049/cdt2.12028
• Languages: English
• ISSNs: 1751-8601

Abstract

Abstract: Fault detection and diagnosis of a Field‐Programmable Gate Array (FPGA) in a short period is vital particularly in reducing the dead time of critical applications that are running on FPGAs. Thus, this paper proposes a new technique that is able to uniquely identify any single stuck‐at fault's location along with the type of fault. Also, the presented technique is able to locate any single pair‐wise bridging fault and distinguish between the two types of common faults. The presented technique uses the Walsh Code method to significantly reduce the number of test configurations when compared with previous methods. Extensive testing of the proposed method is carried out on a series of ISCAS'89 benchmark circuits being implemented in different FPGA families. From the simulation results, the maximum number of configurations needed for interconnect fault detection and diagnosis is log 2 ( n ( n − 1 ) 2 ) + 3 where n is the number of nets under test. It is noted that the proposed method is able to reduce the total number of test configurations by log 2 ( n + 2 ) when compared with previously published methods available in the literature.