A lightweight convolutional neural network hardware implementation for wearable heart rate anomaly detection. (March 2023) - Gu, Minghong; Zhang, Yuejun; Wen, Yongzhong; Ai, Guangpeng; Zhang, Huihong; Wang, Pengjun; Wang, Guoqing
Abstract: In this article, we propose a lightweight and competitively accurate heart rhythm abnormality classification model based on classical convolutional neural networks in deep neural networks and hardware acceleration techniques to address the shortcomings of existing wearable devices for ECG detection. The proposed approach to build a high-performance ECG rhythm abnormality monitoring coprocessor achieves a high degree of data reuse in time and space, which reduces the number of data flows, provides a more efficient hardware implementation and reduces hardware resource consumption than most existing models. The designed hardware circuit relies on 16-bit floating-point numbers for data inference at the convolutional, pooling, and fully connected layers, and implements acceleration of the computational subsystem through a 21-group floating-point multiplicative-additive computational array and an adder tree. The front- and back-end design of the chip was completed on the TSMC 65 nm process. The device has an area of 0.191 mm 2, a core voltage of 1 V, an operating frequency of 20 MHz, a power consumption of 1.1419 mW, and requires 5.12 kByte of storage space. The architecture was evaluated using the MIT-BIH arrhythmia database dataset, which showed a classification accuracy of 97.69% and a classification time of 0.3 ms for a single heartbeat. The hardware architecture offers high accuracy with a simple structure, low resource footprint, and the ability to operate on edge devices with relatively low hardware configurations. Highlights: The highlights in this work are as follow. To construct a high-performance ECG arrhythmia monitoring coprocessor, the proposed data reuse method can reuse data in both time and space, reduce the number of data flow times, which makes the hardware implementation more efficient than most existing models, and reduce hardware resource consumption. Hardware acceleration circuits for the convolutional, pooling, and fully connected layers of the convolutional neural network inference process are designed based on floating-point numbers, and the architecture is evaluated with the MIT-BIH arrhythmia database dataset to demonstrate the performance of the implemented heart rhythm abnormality detection chip. The front-end and back-end design of the chip was completed in TSMC's 65 nm process. The hardware architecture provides high accuracy with a simple architecture, low resource footprint, and the ability to run on edge devices with relatively low hardware configurations.