Trapezoidal reference-based single carrier pulse width modulation method for multilevel converters with novel FPGA implementation. (April 2023)

• Record Type: Journal Article
• Authors: Eroğlu, Fatih; Kurtoğlu, Mehmet
• Is Part Of: Computers & electrical engineering. Volume 107(2023)
• Publication Date: 2023-04
• Subjects: Multilevel converters -- Pulse width modulation -- FPGA implementation -- VHDL programming -- Power quality; Computer engineering -- Periodicals; Electrical engineering -- Periodicals; Electrical engineering -- Data processing -- Periodicals; Ordinateurs -- Conception et construction -- Périodiques; Électrotechnique -- Périodiques; Électrotechnique -- Informatique -- Périodiques; Computer engineering; Electrical engineering; Electrical engineering -- Data processing; Periodicals; Electronic journals; 621.302854
• DOI: 10.1016/j.compeleceng.2023.108650
• Languages: English
• ISSNs: 0045-7906

Abstract

Abstract: Recent attention has focused on trapezoidal reference-based pulse width modulation (PWM) schemes in multilevel converters (MLCs) with easier implementation and better harmonic performance. Nevertheless, these studies utilize trapezoidal reference only for multi carrier PWM methods and details of FPGA implementation are not provided. This paper proposes a trapezoidal reference-based single carrier PWM (TSC-PWM) with its novel FPGA implementation. Design parameters of TSC-PWM is determined such that harmonic performance is maximized and architectural details of FPGA implementation of TSC-PWM are provided. Results reveal that TSC-PWM significantly reduces the resource utilization compared to other methods. Single-phase three-module cascaded H-bridge MLC (CHB-MLC) is established in both simulation and experimental platforms. Results indicate that the TSC-PWM provides better harmonic performance along with higher DC utilization ratio compared to other methods. Moreover, both half-wave and quarter-wave symmetries are ensured with TSC-PWM. Highlights: TSC-PWM is proposed for CHB-MLCs to improve output waveform quality. Both half-wave and quarter-wave symmetries are ensured with proposed gate-decoding. FPGA implementation of TSC-PWM is given with corresponding behavioral models. Superior behavior of TSC-PWM is given in terms of resource utilization within FPGA.