Large‐area monoPoly solar cells on 110 μm thin c–Si wafers with a rear n+poly‐Si/SiOx stack deposited by inline plasma‐enhanced chemical vapour deposition. (20th March 2022)

• Record Type: Journal Article
• Authors: Nandakumar, Naomi; Rodriguez, John W.; Padhamnath, Pradeep; Nampalli, Nitin; Aberle, Armin G.; Duttagupta, Shubham
• Other Names: Hameiri Ziv guestEditor.
• Is Part Of: Progress in photovoltaics. Volume 31:Number 4(2023)
• Page Start: 360
• Page End: 368
• Publication Date: 2022-03-20
• Subjects: industrial process -- large‐area -- monoPoly -- passivated contacts -- PECVD -- screen‐printed -- silicon solar cells -- thin silicon wafer; Solar cells -- Periodicals; Photovoltaic cells -- Periodicals; Solar power plants -- Periodicals; 621.31245
• DOI: 10.1002/pip.3555
• Languages: English
• ISSNs: 1062-7995

Abstract

Abstract: We present an overview of SERIS' monoPoly technology on screen‐printed, M2‐size (244.4 cm 2 ) n ‐type bifacial silicon solar cells with a rear n + :poly‐Si/SiO x passivating contact stack, where the SiO x and n + :poly‐Si layers are fabricated by single‐side inline plasma‐enhanced chemical vapour deposition (PECVD). We demonstrate the application of these stacks on thin (~110 μm) silicon wafers, giving an excellent open‐circuit voltage of 707 mV and an externally verified cell efficiency of 23.2% using commercial screen‐printed and fire‐through metal pastes. A detailed power analysis is presented, with a breakdown of the voltage and current losses. Finally, we share the progress on standard wafers with an efficiency of 23.8% achieved and present the outlook for this technology with a selective passivating contact stack at the front and a full‐area passivating contact stack at the rear. Abstract : We present SERIS' monoPoly technology on thin (~110 µm) silicon wafers with a rear n + :poly‐Si/SiO x passivating contact stack, fabricated by single‐side inline plasma‐enhanced chemical vapour deposition (PECVD). We demonstrate an excellent V OC of 707 mV and an externally verified cell efficiency of 23.2% using commercial screen‐printed and fire‐through metal pastes. A detailed power analysis is presented, with a breakdown of the voltage and current losses, and finally, we share the progress on standard wafers with an efficiency of 23.8% achieved.