PMOS junction optimization for 3D NAND FLASH memory with CMOS under array. (April 2023) - Liao, Jeng-Hwa; Ko, Zong-Jie; Lin, Hsing-Ju; Hsieh, Jung-Yu; Yang, Ling-Wu; Yang, Tahone; Chen, Kuang-Chao; Lu, Chih-Yuan
Highlights: 3D NAND from CNA to CUA suffers Short Channel Effect on P-type MOS since the thermal budget of array would be fully executed on CMOS transistor. A systematic study of the cold carbon implantation on p-type MOS of 3D NAND with CUA is performed. Application of cold carbon implantation on 96 layer 3D NAND with CUA improves MOS characteristics when decreasing the gate length and distance of poly to contact. Abstract: Continuous scaling the 3D NAND technology from CMOS Near Array (CNA) to CMOS Under Array (CUA) can achieve a minimal cell footprint and die size. However, the CMOS performance needs to overcome the short channel effect (SCE) and dopant deactivation since the thermal budget of the array cell would be fully executed on the CMOS transistor when 3D NAND architecture changes from CNA to CUA. Applying Cryogenic technology and carbon co-implantation can boost the CMOS performance by reducing implant induced defects in end of range (EOR) and controlling the interstitials to minimize dopants, such as boron or phosphorus, transient enhanced diffusion (TED) during subsequent thermal process. In this paper, using cold carbon implantation on P-type MOS S/D extension and P-type plug contact process of 96 layer 3D NAND FLASH memory with CUA structure can improve the device characteristics when decreasing the gate length and distance of the poly to contact, such as less SCE and better device On/Off performance. Besides, junction variability improvement is also demonstrated.