A high-efficiency, reliable multilevel hardware-accelerated annealer with in-memory spin coupling and complementary read algorithm. (3rd March 2023) - Wang, Yun-Yuan; Lin, Yu-Hsuan; Lee, Dai-Ying; Lu, Cheng-Hsien; Wei, Ming-Liang; Tseng, Po-Hao; Lee, Ming-Hsiu; Hsieh, Kuang-Yeu; Wang, Keh-Chung; Lu, Chih-Yuan
Abstract: We proposed an in-memory spin coupler based on the 55 nm NOR flash technology to tackle the combinatorial optimization problems. The high-density and cost-effective floating-gate (FG) devices can overcome the capacity limitation in the conventional annealing machines based on static random access memory. In addition, the FG devices featuring high endurance and excellent data retention provide more robust annealing computation as compared to resistive random access memory. A novel complementary read algorithm is further developed to increase the tolerance on threshold voltage ( V th ) variation by 60%. Demonstrations show that the proposed in-memory spin coupling architecture with high efficiency and scalability has great potential for solving the combinatorial optimizations regardless of the problem size.