Development of novel single-die hybridisation processes for small-pitch pixel detectors. (15th March 2023) - Svihra, P.; Braach, J.; Buschmann, E.; Dannheim, D.; Dort, K.; Fritzsch, T.; Kristiansen, H.; Rothermund, M.; Schmidt, J.V.; Vicente Barreto Pinto, M.; Williams, M.
Abstract: Hybrid pixel detectors require a reliable and cost-effective interconnect technology adapted to the pitch and die sizes of the respective applications. During the ASIC and sensor R&D phase, especially for small-scale applications, such interconnect technologies need to be suitable for the assembly of single dies, typically available from Multi-Project-Wafer submissions. Within the CERN EP R&D programme and the AIDAinnova collaboration, innovative hybridisation concepts targeting vertex-detector applications at future colliders are under development. Recent results of two novel interconnect methods for pixel pitches of 25 µm and 55 µm are presented in this contribution — an industrial fine-pitch SnAg solder bump-bonding process adapted to single-die processing using support wafers, as well as a newly developed in-house single-die interconnection process based on Anisotropic Conductive Film (ACF). The fine-pitch bump-bonding process is qualified with hybrid assemblies from a recent bonding campaign at Frauenhofer IZM. Individual CLICpix2 ASICs with 25 µm pixel pitch were bump-bonded to active-edge silicon sensors with thicknesses ranging from 50 µm to 130 µm. The device characterisation was conducted in the laboratory as well as during a beam test campaign at the CERN SPS beam-line, demonstrating an interconnect yield of about 99.7%. The ACF interconnect technology replaces the solder bumps by conductive micro-particles embedded in an epoxy film. The electro-mechanical connection between the sensor and ASIC is achieved via thermocompression of the ACF using a flip-chip device bonder. The required pixel pad topology is achieved with an in-house Electroless Nickel Immersion Gold (ENIG) plating process. This newly developed ACF hybridisation process is first qualified with the Timepix3 ASICs and sensors with 55 µm pixel pitch. The technology can be also used for ASIC-PCB/FPC integration, replacing wire bonding or large-pitch solder bumping techniques. This contribution introduces the two interconnect processes and presents preliminary hybridisation results with CLICpix2 and Timepix3 sensors and ASICs.