Digital cells radiation hardness study of TPSCo 65 nm CIS technology by designing a ring oscillator. (28th February 2023) - Barbero, M.; Barrillon, P.; Fougeron, D.; Habib, A.; Pangaud, P.
Abstract: The CPPM group has long been designing and testing HV-CMOS blocks to complete monolithic chips in various technologies (TJ180, LF150, AMS) in the framework of several collaborations. In 2020, we participated in the MLR1 run in TowerJazz 65 nm technology through CERN's EP-R&D WP1.2, by designing a ring oscillator test chip. Its aim is to characterize the standard cells of this technology and evaluate their radiation hardness against TID. There were 48 ring oscillators formed of different cells with different sizes and two thresholds. In 2022, characterization, temperature, X-ray irradiation (up to more than 500 Mrad) tests and annealing took place, leading to encouraging results presented here.