An FPGA-based readout chip emulator for the CMS ETL detector upgrade. (14th February 2023)

• Record Type: Journal Article
• Authors: Zhang, L.; Edwards, C.; Gong, D.; Huang, X.; Lee, J.; Liu, C.; Liu, T.; Liu, T.; Olsen, J.; Sun, Q.; Wu, J.; Ye, J.; Zhang, W.
• Is Part Of: Journal of instrumentation. Volume 18:Number 2(2023)
• Publication Date: 2023-02-14
• Subjects: Digital electronic circuits -- Front-end electronics for detector readout -- Timing detectors; Scientific apparatus and instruments -- Periodicals; 502.84
• DOI: 10.1088/1748-0221/18/02/C02031
• Languages: English
• ISSNs: 1748-0221

Abstract

Abstract: We present an FPGA-based readout chip emulator board for the CMS Endcap Timing Layer (ETL) detector upgrade. The emulator board uses an Intel Cyclone 10 GX FPGA to emulate the digital functions of four Endcap Layer Readout Chips (ETROCs). Based on the actual ETROC design, the firmware is implemented and verified. The emulator board is being used for the ETROC digital design verification and system development.