A new analytical modelling of 10 nm negative capacitance-double gate TFET with improved cross talk and miller effects in digital circuit applications. (March 2023) - Mukherjee, Adrija; Debnath, Papiya; Nirmal, D.; Chanda, Manash
Abstract: In this paper, the workability of a Negative Capacitance (NC)-Double Gate (DG) Tunnel FET (NC-DGTFET) for digital logic circuit implementation has been detailed. New analytical modelling of the drain current of the NC-DGTEFT considering the band to band tunneling (BTBT), Band tail tunneling (BTT) and Source drain tunneling (SDT) have been investigated. Significant IOÑ 0.025 μA/μm at 250 mV and SS∼12mv/dec - 22mv/dec with very low IOFF (∼fA/μm) is observed with the optimized device. SILVACO ATLAS and MATLAB have been used to validate the proposed model. The modeled NC-DGTFET based Inverter, NAND/NOR has been implemented and the power, delay propagation, and the power delay product (PDP) of the circuit have been analyzed to show the energy efficacy of the NC-DGTFET in the sub-threshold regime (STR) with respect to baseline TFET (B-TFET). To evaluate the impact of the Miller's effects on the digital performances, NC-DGTFET-based five stages Inverter with Fanout = 1 is considered a device under test (DUT) here. Peak overshoot voltage and delay for different fanout and ferroelectric thickness are detailed to show the efficacy of the proposed logic circuits in sub-threshold regime. Both the cross talk and the Miller effects are mitigated significantly in the NC-DGTFET-based digital circuits.