A complementary high linearity bootstrap switch based on negative voltage bootstrap capacitor. (March 2023)

• Record Type: Journal Article
• Authors: Cao, Chao; Zhao, Wei; Fan, Jihui; Zhou, Li; Gan, Zebiao; Duan, Yuhao; Xu, Hui; Guo, Haijun
• Is Part Of: Microelectronics journal. Volume 133(2023)
• Publication Date: 2023-03
• Subjects: Bootstrap switch -- Complementary MOSFET -- Channel charge injection -- Parasitic capacitance -- Dynamic parameters; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2023.105695
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: The sample-and-hold (S/H) circuit is an important part of the analog-to-digital converter (ADC). A bootstrap switch with capacitive load can form a basic S/H circuit. A complementary high linearity gate voltage bootstrap switch based on bootstrap capacitor is proposed in this paper. By reducing the size of the key node transistors, the parasitic capacitance is reduced. The sampling metal-oxide-semiconductor field-effect transistor (MOSFET) in this structure is composed of complementary NMOS and PMOS, which reduces the channel charge injection effect and variations in on-resistance (Ron ). The simulation results show that the effective number of bits (ENOB), signal-to-noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR) of the structure are 16.5 bits, 101.11 dB and 101.83 dB respectively at the sampling frequency of 50 MHz and full swing voltage input of 1.8 V based on SMIC 0.18 μm process. Compared with the conventional NMOS switch, ENOB, SDNR, and SFDR are increased by 2.45 bits, 14.73 dB, and 13.38 dB, respectively. In addition, Monte Carlo (MC) and corner simulations of the proposed circuit are performed, and the results show that the proposed circuit has good performance.