A column-parallel 1-bit ADC with threshold offset reduction technique for single-bit quanta image sensor. (March 2023)

• Record Type: Journal Article
• Authors: Wang, Xiuyu; Ju, Tantan; Liu, Changju; Nie, Kaiming; Xu, Jiangtao
• Is Part Of: Microelectronics journal. Volume 133(2023)
• Publication Date: 2023-03
• Subjects: Threshold offset -- Bit error rate -- 1-Bit ADC -- Quanta image sensor -- Differential charge transfer amplifier -- Calibrated dynamic latch; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2023.105714
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: This paper presents a column-parallel 1-bit analog-to-digital converter (ADC) with threshold offset reduction technique, which aims to reduce the bit error rate (BER) of single-bit quanta image sensor (QIS). The fixed offset of the differential charge transfer amplifier (DCTA) and the fixed compensation offset of the calibrated dynamic latch (CD-latch) comparator are eliminated by two coupling capacitors. Additionally, an improved 3-stage DCTA with low gain error is designed to further suppress the fixed residual offset of the CD-latch. The proposed circuit is implemented by a 110 nm CMOS process. Post-simulation results show that the proposed 1-bit ADC achieves a threshold offset of 32.6 μV at 4 MSa/s sampling rate and 500 μV quantization threshold. Compared with the conventional structure, the random noise of the proposed 1-bit ADC remains almost unaltered. Meanwhile, its threshold offset is lowered by 153.6 μV, making the model BER and circuit BER of the column-level circuit reduce from 2.42% to 0.21% and 2.29%–0.26%, respectively.